1) Field of the Invention
The present invention relates to a driving apparatus for driving a display panel.
2) Description of the Related Art
Recently, a display panel comprising capacitive light emitting elements such as a plasma display panel (hereinafter referred to as PDP) or an electroluminescence display panel is receiving attention as a wall-mounted TV.
FIG. 1 of the accompanying drawings is a diagram showing a schematic structure of the PDP.
In FIG. 1, a PDP 10 has a front substrate (not shown) serving as a display screen and a back substrate (not shown) provided to face the front substrate so as to sandwich a discharge space including a discharge gas between the front and back substrates. On the front substrate, strip-shaped row electrodes X1–Xn and Y1–Yn are alternately formed so as to be aligned parallel with each other. On the back substrate, strip-shaped column electrodes D1–Dm are formed so as to perpendicularly cross each of the row electrodes. The row electrodes X1–Xn and Y1–Yn are configured such that each pair of row electrodes X and Y serves as a display line. The row electrodes X1–Xn and Y1–Yn define the first display line to the n-th display line. Accordingly, a discharge cell serving as a pixel is formed at a crossing portion (including the discharge space) of each pair of row electrodes and each column electrode. Each discharge cell has one of two states, i.e., a light emission state and a non-light emission state, depending on whether an electrical discharge occurs in the discharge cell or not. Specifically, the discharge cell expresses only two luminance gradations, i.e., the lowest luminance (non-light emitting state) and the highest luminance (light emitting state).
Gradation drive using a subfield method is performed in order to achieve a display with halftone luminance which corresponds to an input video signal to the PDP 10 having such discharge cells.
According to the subfield method, each pixel of the input video signal is converted into pixel data of N bits, and a display period of one field (frame) is divided into N subfields (subframes) corresponding to N digits of the N-bit pixel data. The number of discharges corresponding to a weight of the subfield is allocated to the subfield. The discharge is caused only in the subfield which is selected based on the video signal. The halftone luminance corresponding to the video signal is achieved by the overall discharges in one field display period which corresponds to the summation of the number of discharges caused in all the subfields of the frame.
A driving control circuit 50 supplies timing signals to each of an address driver 20, a Y-electrode driver 30 and an X-electrode driver 40, so as to gradation drive the PDP 10 in accordance with the above-mentioned subfield method. Furthermore, the driving control circuit 50 converts each pixel of the input video signal into pixel data of N bits. After dividing the pixel data into N bit digits, the driving control circuit 50 allocates each pixel data bit to the respective subfield which corresponds to the bit digit concerned. Thereafter, the driving control circuit 50 supplies the pixel data bits to the address driver 20 such that the pixel data bits (m bits) per each display line are sequentially supplied at a time in each subfield.
FIG. 2 is a diagram showing various driving pulses and their application timing which are applied to the PDP 10 in each subfield by each of the address driver 20, the Y-electrode driver 30 and the X-electrode driver 40 in accordance with the above-mentioned control operation.
First, in an all-resetting step Rc, the X-electrode driver 40 generates reset pulses RPX of negative polarity and applies the pulses to each of the row electrodes X1–Xn. Furthermore, in the all-resetting step Rc, the Y-electrode driver 30 generates reset pulses RPY of positive polarity and simultaneously applies the pulses to each of the row electrodes Y1–Yn. All discharge cells in the PDP 10 are reset-discharged in response to the application of the reset pulses RPX and RPY and wall charges of a predetermined amount are uniformly formed in each discharge cell. All of the discharge cells are, thus, initialized to a light emitting cell state.
In a pixel data writing step Wc, the address driver 20 sequentially converts the pixel data bits (m bits), which are sequentially supplied per each display line at a time, into m pixel data pulses. For example, the address driver 20 generates the pixel data pulse of a high voltage when the pixel data bit is a logic level 1, whereas the address driver 20 generates the pixel data pulse of a low voltage (0 volt) when the pixel data bit is a logic level 0. Then, the address driver 20 sequentially applies the pixel data pulse groups DP1, DP2, DP3, . . . , and DP(n), which are formed by grouping the pixel data pulses per each display line (m pulses), to the column electrodes D1–Dm as shown in FIG. 2. Furthermore, in each application timing, the Y-electrode driver 30 sequentially applies scan pulses SP of negative polarity as shown in FIG. 2 to the row electrodes Y1–Yn, in synchronization with the application timing of each of the pixel data pulse groups DP. In this instance, a discharge (selective erasure discharge) occurs only in the discharge cells in crossing portions of the row electrodes to which the scan pulses SP have been applied and the column electrodes to which the high voltage pixel data pulses DP have been applied, and the wall charges remaining in those discharge cells are erased. Accordingly, the discharge cells initialized to the light emitting cell state in the all-resetting step Rc are shifted to the non-light emitting cell state. On the other hand, the selective erasure discharge does not occur in the discharge cells where the pixel data pulses DP of the low voltage have been applied, even though the scan pulses SP have been applied thereto. Thus the initialized state in the all-resetting step Rc, namely, the light emitting cell state is maintained.
In a light emission sustaining step Ic, the X-electrode driver 40 repetitively applies sustain pulses IPX of positive polarity to the row electrodes X1–Xn as shown in FIG. 2. Furthermore, in the light emission sustaining step Ic, the Y-electrode driver 30 repetitively applies sustain pulses IPY of positive polarity to the row electrodes Y1–Yn with a difference in the application timing from the sustain pulses IPX. In this instance, only the discharge cells in which the wall charges remain, i.e., only the discharge cells in the light emitting cell state, discharge (sustain-discharge) every time the sustain pulses IPX and IPY are alternately applied. Specifically, only the discharge cells set to the light emitting cell state during the pixel data writing step Wc repeat the light emission due to the sustain-discharge, with the number of applications corresponding to the weight of this subfield, and sustain the light emitting state. The number of applications of the sustain pulses IPX and IPY has been previously setup in accordance with the weight of the subfield concerned.
In an erasing step E, the Y-electrode driver 30 applies erasing pulses EP to the row electrodes Y1–Yn as shown in FIG. 2. All of the discharge cells are, thus, allowed to erasure-discharge at once, thereby extinguishing the wall charges remaining in the discharge cells.
By executing the above-mentioned series of operations a plurality of times in each field, the halftone luminance can be visually recognized which corresponds to the total number of the sustain discharges generated in the light emission sustaining step Ic in the subfields of that field.
According to the driving operation, a discharge current due to the sustain discharge flows to the Y-electrode driver 30 via a current channel including the X-electrode driver 40, the row electrodes X1–Xn and the row electrodes Y1–Yn during a rising period of the sustain pulses IPX. On the other hand, a discharge current flows to the X-electrode driver 40 via a current channel including the Y-electrode driver 30, the row electrodes Y1–Yn and the row electrodes X1–Xn during a rising period of the sustain pulses IPY. Specifically, the current flow behavior of the discharge current from the row electrodes X1–Xn to the row electrodes Y1–Yn and the other current flow behavior of the discharge current from the row electrodes Y1–Yn to the row electrodes X1–Xn are alternately repeated in the light emission sustaining step Ic. In this instance, when the sustain discharge is generated in one of the discharge cells on the display line, the discharge current flows between a pair of the row electrodes X and Y serving as such display line. Specifically, when the sustain pulses IPX (or IPY) are simultaneously applied to the row electrodes X1–Xn (or Y1–Yn) as shown in FIG. 2, the discharge currents are likely to flow from each of the row electrodes X (or Y) to each of the row electrodes Y (or X) at once. Accordingly, when the currents flow through a large number of the display lines in the same direction, an unnecessary electromagnetic radiation is likely to increase due to the generation of a strong magnetic field within the panel surface.